1. Field
The present invention is directed toward the field of data communications, and more particularly toward clock and data recovery techniques.
2. Art Background
Electronic circuits utilize serial data transmission to transmit data among one or more circuits. In general, serial data transmission involves transmitting bits in a single bit stream at a predetermined data rate. The data rate is expressed as the number of bits transmitted per second (“bps”). Typically, to transfer data between circuits, the sending circuit employs a transmitter that modulates and sends data using a local clock. The local clock provides the timing for the bit rate. The receiving circuit employs a receiver to recover the data, and in some cases, the clock. The receiver circuit recovers the serial bit stream of data by sampling the bit stream at the specified data rate.
Techniques have been developed in an attempt to maximize the efficiency of serial data transfer. Some techniques recover the data at the receiver without receiving the sampling clock from the transmitter (i.e., a separate clock is generated at the receiver). For example, serial data links “over sample” the data to recover clock and data. In one over sampling method, the incoming data is first sampled at the bit cycle transition point to determine whether the phase of the clock at the receiver leads or lags the phase of the bit transitions in the serial bit stream. In addition, the serial bit stream is sampled at the center of the bit cycle to determine the state or value of the data for that bit cycle. Other techniques to recover the clock at the receiver from a serial bit stream include interpolating clock and data recovery and a conventional voltage controlled oscillator (“VCO”) based techniques.
These clock and data recovery techniques require one or more reference clocks. For example, the over sampling method requires a reference clock circuit to generate multiple reference clocks. Each reference clock has a different phase for sampling the input data stream. Typically, the reference clocks are generated with the use of expensive crystal oscillators (“XOs”) or voltage controlled crystal oscillators (“VCXOs”). It is desirable to reduce or eliminate the need for expensive reference clock sources in a clock and data recovery circuit.
Some clock and data recovery circuits employ a clean-up clock circuit. The clean-up clock circuit filters high frequency components on the clock recovered from the clock and data recovery circuit. The cleaned-up clock (the output of the clean-up clock circuit) is subsequently used in applications that require low jitter in the clock signal. The clean-up circuit is typically implemented using an integrated circuit external to the clock and data recovery circuit plus a voltage controlled crystal oscillator. It is desirable to use a clean-up clock circuit without adding an additional integrated circuit to the receiver. It is also desirable to use a clean-up clock circuit without requiring an additional clock source, such as a voltage controlled crystal oscillator.